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7630 Datasheet(PDF) 36 Page - Renesas Technology Corp |
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7630 Datasheet(HTML) 36 Page - Renesas Technology Corp |
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36 / 238 page  1-20 7630 Group User’s Manual +$5':$5( Fig. 17 Structure of interrupt request and control registers A, B and C 7 Interrupt request register A (address 000216) IREQA CAN wake up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit 7 0 7 0 0 : No interrupt request 1 : Interrupt requested 0 Not used (returns to ”0” when read) External interrupt INT0 request bit External interrupt INT1 request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit Interrupt request register B (address 000316) IREQB Interrupt request register C (address 000416) IREQC UART receive complete (receive buffer full) interrupt request bit UART transmit complete (transmit register empty) interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I/O interrupt request bit AD conversion complete interrupt request bit Key-on wake-up interrupt request bit Not used (returns to ”0” when read) 7 0 Not used (returns to ”0” when read) External interrupt INT0 enable bit External interrupt INT1 enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit Interrupt control register A (address 000516) ICONA 7 0 Interrupt control register B (address 000616) ICONB CAN wake–up interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit 7 0 Interrupt control register C (address 000716) ICONC UART receive complete (receive buffer full) interrupt enable bit UART transmit complete (transmit register empty) interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive error interrupt enable bit Serial I/O interrupt enable bit AD conversion complete interrupt enable bit Key-on wake-up interrupt enable bit Not used (returns to ”0” when read) 0: Interrupt disabled 1: Interrupt enabled INTERRUPTS |
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