7630 datasheet(87/238 Pages) RENESAS

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APPLICATION

2.3 Timers

2-21

7630 Group User’s Manual

Fig. 2.3.6 Structure of Timer X mode register

Fig. 2.3.7 Structure of Timer Y mode register

Timer X mode register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Timer X mode register (TXM) [Address : 001E16]

Timer X mode bits

Timer X stop control bit

b5 b4

0 0 : Timer mode

0 1 : Bi-phase counter mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

Not used (“0” when read, don't write “1”.)

Timer X data write control bit

0 : Data is written to latch and timer.

1 : Data is written to latch only.

0 : For event counter mode,

rising edge active

For interrupt request,

falling edge active

For pulse width measurement mode,

measure “H” period

1 : For event counter mode,

falling edge active

For interrupt request,

rising edge active

For pulse width measurement mode,

measure “L” period

CNTR0 polarity selection bit

0 : Timer counting

1 : Timer stopped

Timer Y mode register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Timer Y mode register (TYM) [Address : 001F16]

Timer Y operation mode bits

Timer Y stop control bit

b5 b4

0 0 : Timer mode

0 1 : Pulse period measurement mode

1 0 : Event counter mode

1 1 : H/L pulse width measurement mode

Timer X count source selection

bits

0 : For event counter mode,

rising edge active

For interrupt request,

falling edge active

For pulse period measurement mode,

refer to falling edge

1 : For event counter mode,

falling edge active

For interrupt request,

rising edge active

For pulse period measurement mode,

refer to rising edge

CNTR1 polarity selection bit

0 : Timer counting

1 : Timer stopped

b1 b0

0 0 :

φ divided by 4 (Note)

0 1 :

φ divided by 16 (Note)

1 0 :

φ divided by 64 (Note)

1 1 :

φ divided by 128 (Note)

Timer Y count source selection

bits

b3 b2

0 0 :

φ divided by 2 (Note)

0 1 :

φ divided by 8 (Note)

1 0 :

φ divided by 32 (Note)

1 1 :

φ divided by 64 (Note)

Note: The internal system clock

φ is divided f(XIN) by 2 or by 8. The division ratio is decided by

the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ).

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