7630 datasheet(77/238 Pages) RENESAS

77 / 238 page

2-11

7630 Group User’s Manual

APPLICATION

2.2 Interrupts

Fig. 2.2.4 Structure of Interrupt request register C

Fig. 2.2.5 Structure of Interrupt control register A

Interrupt request register C

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Interrupt request register C (IREQC) [Address : 000416]

Not used (“0” when read.)

UART receive complete (receive

buffer full) interrupt request bit

0 : No interrupt request

1 : Interrupt requested

UART transmit complete (transmit

0 : No interrupt request

1 : Interrupt requested

UART transmit buffer empty

interrupt request bit

0 : No interrupt request

1 : Interrupt requested

UART receive error

interrupt request bit

0 : No interrupt request

1 : Interrupt requested

Serial I/O interrupt request bit

0 : No interrupt request

1 : Interrupt requested

AD conversion complete

interrupt request bit

0 : No interrupt request

1 : Interrupt requested

Key-on wake-up

interrupt request bit

0 : No interrupt request

1 : Interrupt requested

V Can be cleared to “0” by software, but cannot be set to “1”.

Interrupt control register A

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Interrupt control register A (ICONA) [Address : 000516]

Not used (“0” when read.)

External interrupt INT0 enable bit

0 : Interrupt disabled

1 : Interrupt enabled

External interrupt INT1 enable bit

CAN successful transmission

interrupt enable bit

CAN successful receive

interrupt enable bit

CAN overrun

interrupt enable bit

CAN error passive

interrupt enable bit

CAN bus off

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

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