7630 datasheet(33/238 Pages) RENESAS

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7630 Group User’s Manual

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INTERRUPTS

There are 24 interrupts: 6 external, 17 internal, and 1 software.

Interrupt Control

Each interrupt except the BRK instruction interrupt has both an inter-

rupt request bit and an interrupt enable bit, and is controlled by the

interrupt disable flag. An interrupt occurs when the corresponding

interrupt request and enable bits are “1” and the interrupt disable flag

is “0”. Interrupt enable bits can be cleared or set by software. Inter-

rupt request bits can be cleared by software but cannot be set by

software. The BRK instruction interrupt and reset cannot be disabled

with any flag or bit. The I flag disables all interrupts except the BRK

instruction interrupt and reset. If several interrupt requests occur at

the same time, the interrupt with the highest priority is accepted first.

Interrupt Operation

Upon acceptance of an interrupt, the following operations are auto-

matically performed.

The processing being executed is stopped.

The contents of the program counter and processor status

Concurrently with the push operation, the interrupt jump

destination address is read from the vector table into the

program counter.

The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

Notes on use

When the active edge of an external interrupt (INT0, INT1, CNTR0,

CNTR1, CWKU or KOI) is changed, the corresponding interrupt

request bit may also be set. Therefore, take the following sequence.

(1) Disable the external interrupt which is selected.

(2) Change the active edge in interrupt edge selection register.

(in the case of CNTR0: Timer X mode register; in the case of

CNTR1: Timer Y mode register)

(3) Clear the interrupt request bit to “0”.

(4) Enable the external interrupt which is selected.

INTERRUPTS

7630 Datasheet(PDF) 33 Page - Renesas Technology Corp