7630 datasheet(11/238 Pages) RENESAS

11 / 238 page

List of figures

7630 GROUP USER’S MANUAL

Fig. 48 Ceramic resonator circuit ........................................................................................ 1-43

Fig. 49 Block diagram of clock generating circuit ............................................................. 1-43

Fig. 50 Programming and testing of One Time PROM version ...................................... 1-44

Fig. 51 Circuit for measuring output switching characteristics ........................................ 1-49

Fig. 52 Timing diagram ......................................................................................................... 1-50

CHAPTER 2. APPLICATION

Fig. 2.1.1 Memory map of I/O port related registers .......................................................... 2-2

Fig. 2.1.2 Structure of Port Pi register (i = 0, 1, 2, 3, 4) ................................................. 2-3

Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ................................. 2-3

Fig. 2.1.4 Structure of Port Pi pull-up register (i = 0, 2) ................................................... 2-4

Fig. 2.1.5 Structure of Port P1 pull-up register ................................................................... 2-4

Fig. 2.1.6 Structure of Port P3 pull-up control register ...................................................... 2-5

Fig. 2.1.7 Structure of Port P4 pull-up/down control register ............................................ 2-5

Fig. 2.1.8 Structure of Porarity control register ................................................................... 2-6

Fig. 2.1.9 External circuit example applying overvoltage to digital inputs ....................... 2-7

Fig. 2.2.1 Memory map of interrupt related registers ......................................................... 2-9

Fig. 2.2.2 Structure of Interrupt request register A ........................................................... 2-10

Fig. 2.2.3 Structure of Interrupt request register B ........................................................... 2-10

Fig. 2.2.4 Structure of Interrupt request register C .......................................................... 2-11

Fig. 2.2.5 Structure of Interrupt control register A ............................................................ 2-11

Fig. 2.2.6 Structure of Interrupt control register B ............................................................ 2-12

Fig. 2.2.7 Structure of Interrupt control register C ............................................................ 2-12

Fig. 2.2.8 Structure of Interrupt polarity selection register .............................................. 2-13

Fig. 2.2.9 Structure of Polarity control register ................................................................. 2-13

Fig. 2.2.10 Interrupt setting method (1) .............................................................................. 2-14

Fig. 2.2.11 Interrupt setting method (2) .............................................................................. 2-15

Fig. 2.2.12 Setting method for registers related to key-on wake-up interrupt (1) ........ 2-16

Fig. 2.2.13 Setting method for registers related to key-on wake-up interrupt (2) ........ 2-17

Fig. 2.3.1 Memory map of timer related registers ............................................................. 2-18

Fig. 2.3.2 Structure of Timer 1, Timer 3 ............................................................................ 2-19

Fig. 2.3.3 Structure of Timer 2 ............................................................................................ 2-19

Fig. 2.3.4 Structure of Timer 123 mode register ............................................................... 2-20

Fig. 2.3.5 Structure of Timer XL, Timer XH, Timer YL, Timer YH ................................. 2-20

Fig. 2.3.6 Structure of Timer X mode register .................................................................. 2-21

Fig. 2.3.7 Structure of Timer Y mode register .................................................................. 2-21

Fig. 2.3.8 Timers connection and division ratios [Clock function] .................................. 2-23

Fig. 2.3.9 Setting of related registers [Clock function] ..................................................... 2-24

Fig. 2.3.10 Control procedure [Clock function] .................................................................. 2-25

Fig. 2.3.11 A method for judging if input pulse exists ..................................................... 2-26

Fig. 2.3.12 Setting of related registers [Measurement of frequency] (1) ....................... 2-27

Fig. 2.3.13 Setting of related registers [Measurement of frequency] (2) ....................... 2-28

Fig. 2.3.14 Control procedure [Measurement of frequency] ............................................ 2-29

Fig. 2.3.15 Timer connection and division ratios [Measurement of pulse width] .......... 2-30

Fig. 2.3.16 Setting of related registers [Measurement of pulse width] .......................... 2-31

Fig. 2.3.17 Control procedure [Measurement of pulse width] (1) ................................... 2-32

Fig. 2.3.18 Control procedure [Measurement of pulse width] (2) ................................... 2-33

Fig. 2.4.1 Block diagram of CAN module ........................................................................... 2-35

Fig. 2.4.2 Memory map of CAN related registers ............................................................. 2-36

Fig. 2.4.3 Structure of CAN transmit control register ....................................................... 2-37

Fig. 2.4.4 Structure of CAN bus timing control register 1 ............................................... 2-37

Fig. 2.4.5 Structure of CAN bus timing control register 2 ............................................... 2-38

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