7630 datasheet(56/238 Pages) RENESAS

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7630 Group User’s Manual

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WATCHDOG TIMER

The watchdog timer consists of two separate counters: one 7-bit

counter (WDH) and one 4-bit counter (WDL). Cascading both

counters or using the high-order counter allows only to select the

time-out from either 524288 or 32768 cycles of the internal clock

φ.

Refer to Fig. 43 and Fig. 44. Both counters are addressed by the

same watchdog timer register (WDT). When writing to this register,

both counters will be set to the following default values:

•

the high-order counter will be set to address 7F16

•

the low-order counter will be set to address F16

regardless of the data written to the WDT register. Reading the

watchdog timer register will return the corresponding control bit sta-

tus, not the counter contents.

Once the WDT register is written to, the watchdog timer starts count-

ing down and the watchdog timer interrupt is enabled. Once it is run-

ning, the watchdog timer cannot be disabled or stopped except by

reset. On a watchdog timer underflow, a non-maskable watchdog

timer interrupt will be requested.

To prevent the system being stopped by STP instruction, this instruc-

tion can be disabled by the STP instruction disable bit of WDT regis-

ter. Once the STP instruction is disabled, it cannot be enabled again

except by RESET.

Fig. 43 Block diagram of watchdog timer

Fig. 44 Structure of watchdog timer register (

φ is internal clock system)

1/256

WDT interrupt

WDL counter (4)

WDH counter (7)

WDT7

“F16”“7F16”

WDT register (8)

“1”

“0”

Not used (undefined when read)

Stop instruction disable bit

0 : Stop instruction enabled

1 : Execute two NOP instructions instead (once this bit is set to

“1” it can‘t be cleared to “0” again, except on RESET.)

Upper byte count source selection bit

0 : Underflow of the low order counter

1 :

φ divided by 256

Watchdog timer register (address 002E16)

WDT

WATCHDOG TIMER

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