7630 datasheet(86/238 Pages) RENESAS

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2-20

7630 Group User’s Manual

APPLICATION

2.3 Timers

Fig. 2.3.4 Structure of Timer 123 mode register

Fig. 2.3.5 Structure of Timer XL, Timer XH, Timer YL, Timer YH

Timer 123 mode register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Timer 123 mode register (T123M) [Address : 001916]

PWM output enable bit

0 : PWM output disabled

1 : PWM output enabled

Timer 2 write control bit

Timer 2 count source selection bit

Timer 3 count source selection bit

Pre-divider division ratio bits

0 : Latch and counter

1 : Latch only

0 : Timer 1 underflow

1 : Pre-divider output

0 : Timer 1 underflow

1 : Pre-divider output

b7 b6

0 0 :

φ divided by 1 (Note)

0 1 :

φ divided by 8 (Note)

1 0 :

φ divided by 32 (Note)

1 1 :

φ divided by 128 (Note)

Not used (“0” when read, don't write “1”.)

PWM polarity selection bit

0 : Start on “H” level output

1 : Start on “L” level output

Note: The internal system clock

φ is divided f(XIN) by 2 or by 8. The division ratio is decided by

the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ).

Timer XL, Timer XH, Timer YL, Timer YH

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Timer XL (TXL), Timer XH (TXH) [Address : 001A16, 001B16]

Timer YL (TYL), Timer YH (TYH) [Address : 001C16, 001D16]

q Set “000016” to “FFFF16” as timer count value.

q Write access

The timer value is written to Timer X or Timer Y and latch at

the same timer or to the latch only (Note).

Write first low byte (TXL, TYL) and then high byte (TXH, TYH).

q Read access

To get the actual Timer X or Timer Y value read out the

corresponding timer register.

A measurement value is read out in pulse period and pulse

width measurement mode.

Read first high byte (TXH, TYH) and then low byte (TXL, TYL).

Note: Depinding on the Timer X or Timer Y data write control bit (bit 0 of the Timer X or

Timer Y mode register [address: 001E16, 001F16] ).

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