7630 datasheet(45/238 Pages) RENESAS

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1-29

7630 Group User’s Manual

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Fig. 27 Structure of serial I/O control register (

φ is internal system clock)

Clock Asynchronous Serial I/O (UART)

The UART is a full duplex asynchronous transmit/receive unit. The

built-in clock divider and baud rate generator enable a broad range of

transmission speeds. Please refer to Block diagram of UART.

(1) Description

The transmit and receive shift registers have a buffer (consisting of

high and low order byte) each. Since the shift registers cannot be

written to or read from directly, transmit data is written to the transmit

buffer and receive data is read from the receive buffer. A transmit or

receive operation will be triggered by the transmit enable bit and

receive enable bit of the UART control register UCON (see Structure

of UART control register). The double function terminals P25/UTXD,

P26/URTS and P24/URXD, P27/UCTS will be switched to the UART

pins automatically.

(2) Baud rate selection

The baud rate of transmission and reception is determined by the

setting of the prescaler and the contents of the UART baud rate gen-

erator register. It is calculated by:

where

p is the division ratio of the prescaler and n is the contents of

the UART baud rate generator register. The prescalers division ration

can be selected by the UART mode register (see page 1-31).

UART mode register (UMOD, Structure of UART

mode register)

The UART mode register allows to select the transmission and

reception format with the following options:

•

word length: 7, 8 or 9 bits

•

parity: none, odd or even

•

stop bits: 1 or 2

It allows to select the prescalers division ratio as well.

UART baud rate generator (UBRG)

This 8 bit register allows to select the baud rate of the UART (see

above). Set this register to the desired value before enabling recep-

tion or transmission.

UART control register (UCON, Structure of UART

control register)

The UART control register consists of four control bits (bit 0 to bit 3)

which allow to control reception and transmission.

UART status register (USTS, Structure of UART sta-

tus register)

The read-only UART status register consists of 7 bits (bit 0 to bit 6)

which indicate the operating status of the UART function and various

errors.

Clock divider selection bits

b2 b1 b0

000 :

φ divided by 4

001 :

φ divided by 8

010 :

φ divided by 16

01 1 :

φ divided by 32

100 :

φ divided by 64

101 :

φ divided by 128

11 0 :

φ divided by 256

111 :

φ divided by 512

P20/SIN, P21/SOUT and P22/SCLK function selection bit

0 : I/O port function

1 : SI/O function

P23/SRDY function selection bit

0 : I/O port function

1 : SI/O function

Transmission order selection bit

0 : LSB first

1 : MSB first

Synchronization clock selection bit

0 : Use external clock

1 : Use internal clock

Not used (“0” when read)

SIO control register (address 001316)

SIOCON

16 pn

()

⋅⋅

-----------------------------------

SERIAL I/Os

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