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7630 Datasheet(PDF) 42 Page - Renesas Technology Corp |
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7630 Datasheet(HTML) 42 Page - Renesas Technology Corp |
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42 / 238 page ![]() 1-26 7630 Group User’s Manual +$5':$5( TIMER 1, TIMER 2, TIMER 3 Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com- mon pre-divider. Timer 1 can operate in the timer mode only, whereas timers 2 and 3 can be used to generate a PWM output signal timing as well. Timers 1 to 3 are down count timers. See Fig. 23. Fig. 23 Block diagram of timers 1 to 3 ( φ is internal system clock) Timer 1 The count source of timer 1 is the output of timer 123 pre-divider. The division ratio of the pre-divider can be selected by the pre-divider divi- sion ratio bits of timer 123 mode register (T123M). Refer to Timer 123 mode register configuration (f is internal system clock). On a timer 1 underflow, the timer 1 interrupt request bit will be set to “1”. Writing to timer 1 initializes the latch and counter. Timers 2 and 3 The count source of timers 2 and 3 can be either the output of the timer 123 pre-divider or the timer 1 underflow. The count source can be selected by the timer count source selection bits of timer 123 mode register (T123M). Writing to timer 2 register affects the reload latch only or both of the reload latch and counter depending on the timer 2 write control bit of T123M. When the timer write control bit is set to “0”, both latch and counter will be initialized simultaneously; when set to “1” only the reload latch will be initialized, on an underflow, the counter will be set to the modified reload value. Writing to timer 3 initializes latch and counter both. Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit to be set to “1”. T123M0 1 1/8 1/32 1/128 T123M67 φ T1 counter (8) T1 latch (8) T2 counter (8) T2 latch (8) T3 counter (8) T3 latch (8) T1 interrupt T2 interrupt T3 interrupt S R Q S R Q T123M3 T123M4 T123M1 T123M1 S TQ P16/PWM P16 latch P1D6 T123M1 “00 ” “01” “10” “11” “1” “0” “0” “1” “1” “0” “0” “1” TIMERS |
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