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PCM5310PAPR Datasheet(PDF) 73 Page - Texas Instruments |
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PCM5310PAPR Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 103 page  Register 94 (5Eh) Register 95 (5Fh) Register 101 (65h) PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 94 5Eh Master/slave interface format for ADC34 AMS34[3:0] HF34 RSV AFM34[1:0] AMS34[3:0]: Master/Slave Audio Interface Setting for ADC34 These bits set the master or slave mode. ADC34 receives LRCK and BCK from PORT-1, PORT-2, PORT-3, PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode. Default value: 1000 MASTER/SLAVE AUDIO INTERFACE SETTING FOR MASTER/SLAVE AUDIO INTERFACE SETTING FOR AMS34[3:0] ADC34 AMS34[3:0] ADC34 0000 Reserved 1000 Slave and system clock fS auto-detect mode (default) 0001 Master and system clock 768 fS 1001 Slave and system clock 768 fS 0010 Master and system clock 512 fS 1010 Slave and system clock 512 fS 0011 Master and system clock 384 fS 1011 Slave and system clock 384 fS 0100 Master and system clock 256 fS 1100 Slave and system clock 256 fS 0101 Reserved 1101 Reserved 0110 Reserved 1110 Reserved 0111 Reserved 1111 Reserved HF34: High-Pass Filter Disable for ADC34 This bit disables the digital high-pass filter of ADC34. Default value: 0 0 (0.019 fS/1000) Hz (default) 1 Off AFM34[1:0]: Audio Interface Format for ADC34 These bits select the ADC34 audio data format as I2S, right-justified, or left-justified. Default value: 00 00 16 to 24 bits, I2S (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 95 5Fh Power up/down for ADC34 PA34 RSV RSV RSV RSV RSV RSV RSV PA34: Power Up/Down Control for ADC34 This bit controls the power up/down for ADC34, including the decimation filter. Default value: 1 0 Power up 1 Power down (default) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 101 65h LRCK/BCK selection of PORT-1 and PORT-2 LBS2[3:0] LBS1[3:0] Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 73 Product Folder Link(s): PCM5310 |
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