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PCM5310PAPR Datasheet(PDF) 82 Page - Texas Instruments |
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PCM5310PAPR Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 103 page  Register 107 (6Bh) LRCK6 BCK6 LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK,BCKfromADC12atMaster LRCK,BCKfromADC34atMaster LRCK,BCKfromDAC12atMaster DATAfromGPIO1 DATAfromADC12 LRCK,BCKfromDAC34atMaster DATAfromGPIO2 DATAfromADC34 SCK6 SCK1 SCK2 SCK3 DATA6 DATA1 DATA2 DATA3 LRCK/BCKtoMUX_ADCxxandMUXDACxx SCKtoMUX_ADCxxandMUXDACxx DATAtoMUXDACxx LRCK4 BCK4 LRCK5 BCK5 SCK4 SCK5 DATA4 DATA5 Register108 DTS6[3:0] Register109 SCS6[2:0] Register107 LBS6[3:0] PORT-6 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 107 6Bh LRCK/BCK selection of PORT-5 and PORT-6 LBS6[3:0] LBS5[3:0] LBS6[3:0]: LRCK/BCK Selection of PORT-6 (MUX_P6BL) These bits are used for routing LRCK and BCK of PORT-6. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-6. Figure 51 shows a detailed diagram of PORT-6. Default value: 0101 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Input LRCK6 and BCK6 (default) 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved Figure 51. Detailed Diagram of PORT-6 82 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 |
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