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PCM5310PAPR Datasheet(PDF) 74 Page - Texas Instruments |
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PCM5310PAPR Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 103 page ![]() LRCK2 BCK2 LRCK1 BCK1 LRCK3 BCK3 LRCK4 BCK4 LRCK,BCKfromADC12atMaster LRCK,BCKfromADC34atMaster LRCK,BCKfromDAC12atMaster DATAfromGPIO1 DATAfromADC12 LRCK,BCKfromDAC34atMaster DATAfromGPIO2 DATAfromADC34 SCK2 SCK1 SCK3 SCK4 DATA2 DATA1 DATA3 DATA4 LRCK/BCKtoMUX_ADCxxandMUXDACxx SCKtoMUX_ADCxxandMUXDACxx DATAtoMUXDACxx LRCK5 BCK5 LRCK6 BCK6 SCK5 SCK6 DATA5 DATA6 Register102 DTS2[3:0] Register103 SCS2[2:0] Register101 LBS2[3:0] PORT-2 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com LBS2[3:0]: LRCK/BCK Selection of PORT-2 (MUX_P2BL) These bits are used for routing LRCK and BCK of PORT-2. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-2. Figure 47 shows a detailed diagram of PORT-2. Default value: 0001 0000 Output LRCK1 and BCK1 0001 Input LRCK2 and BCK2 (default) 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved Figure 47. Detailed Diagram of PORT-2 74 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 |
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