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PCM5310PAPR Datasheet(PDF) 75 Page - Texas Instruments |
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PCM5310PAPR Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 103 page ![]() LRCK, BCKfrom ADC12atMaster LRCK, BCKfrom ADC34atMaster LRCK, BCKfrom DAC12atMaster LRCK, BCKfrom DAC34atMaster DATA from ADC12 DATA from ADC34 LRCK/BCKtoMUX_ADCxx andMUXDACxx PORT-1 SCKtoMUX_ADCxx andMUXDACxx DATAtoMUXDACxx DAT A from GPIO1 DAT A from GPIO2 Register101 LBS1[3:0] Register103 SCS1[2:0] Register102 DTS1[3:0] LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK4 BCK4 LRCK5 BCK5 LRCK6 BCK6 SCK1 SCK2 SCK3 SCK4 SCK5 SCK6 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 LBS1[3:0]: LRCK/BCK Selection of PORT-1 (MUX_P2BL) These bits are used for routing LRCK and BCK of PORT-1. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-1. Figure 48 shows a detailed diagram of PORT-1. Default value: 0000 0000 Input LRCK1 and BCK1 (default) 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved Figure 48. Detailed Diagram of PORT-1 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 75 Product Folder Link(s): PCM5310 |
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