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PCM5310PAPR Datasheet(PDF) 83 Page - Texas Instruments |
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PCM5310PAPR Datasheet(HTML) 83 Page - Texas Instruments |
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83 / 103 page ![]() LRCK5 BCK5 LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK,BCKfromADC12atMaster LRCK,BCKfromADC34atMaster LRCK,BCKfromDAC12atMaster DATAfromGPIO1 DATAfromADC12 LRCK,BCKfromDAC34atMaster DATAfromGPIO2 DATAfromADC34 SCK5 SCK1 SCK2 SCK3 DATA5 DATA1 DATA2 DATA3 LRCK/BCKtoMUX_ADCxxandMUXDACxx SCKtoMUX_ADCxxandMUXDACxx DATAtoMUXDACxx LRCK4 BCK4 LRCK6 BCK6 SCK4 SCK6 DATA4 DATA6 Register108 DTS5[3:0] Register109 SCS5[2:0] Register107 LBS5[3:0] PORT-5 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 LBS5[3:0]: LRCK/BCK Selection of PORT-5 (MUX_P5BL) These bits are used for routing LRCK and BCK of PORT-5. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-5. Figure 52 shows a detailed diagram of PORT-5. Default value: 0100 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Input LRCK5 and BCK5 (default) 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved Figure 52. Detailed Diagram of PORT-5 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 83 Product Folder Link(s): PCM5310 |
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