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PCM5310PAPR Datasheet(PDF) 79 Page - Texas Instruments |
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PCM5310PAPR Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 103 page  LRCK3 BCK3 LRCK1 BCK1 LRCK2 BCK2 LRCK4 BCK4 LRCK,BCKfromADC12atMaster LRCK,BCKfromADC34atMaster LRCK,BCKfromDAC12atMaster DATAfromGPIO1 DATAfromADC12 LRCK,BCKfromDAC34atMaster DATAfromGPIO2 DATAfromADC34 SCK3 SCK1 SCK2 SCK4 DATA3 DATA1 DATA2 DATA4 LRCK/BCKtoMUX_ADCxxandMUXDACxx SCKtoMUX_ADCxxandMUXDACxx DATAtoMUXDACxx LRCK5 BCK5 LRCK6 BCK6 SCK5 SCK6 DATA5 DATA6 Register105 DTS3[3:0] Register106 SCS3[2:0] Register104 LBS3[3:0] PORT-3 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 LBS3[3:0]: LRCK/BCK Selection of PORT-3 (MUX_P3BL) These bits are used for routing LRCK and BCK of PORT-3. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-3. Figure 50 shows a detailed diagram of PORT-3. Default value: 0010 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Input LRCK3 and BCK3 (default) 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved Figure 50. Detailed Diagram of PORT-3 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 79 Product Folder Link(s): PCM5310 |
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