82G33 datasheet(334/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

334

Datasheet

9.4.1

ID—Identification

B/D/F/Type:

0/3/3/PCI

Address Offset:

00-03h

Default Value:

29C78086h

Access:

Size:

32 bits

This register combined with the Device Identification register uniquely identifies any

PCI device.

Bit

Access &

Default

Description

31:16

29C7h

Device ID (DID): Assigned by manufacturer, identifies the device

15:0

8086h

Vendor ID (VID): 16-bit field which indicates the company vendor as

Intel

9.4.2

CMD—Command Register

B/D/F/Type:

0/3/3/PCI

Address Offset:

04-05h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

This register provides basic control over the device's ability to respond to and perform

Host system related accesses.

Note: Reset: Host System reset or D3->D0 transition.

Bit

Access &

Default

Description

15:11

00h

Reserved

Interrupt Disable (ID): This bit disables pin-based INTx# interrupts.

This bit has no effect on MSI operation.

0 = Enable. Internal INTx# messages are generated if there is an

interrupt and MSI is not enabled.

1 = Disable. Internal INTx# messages will not be generated.

Fast back-to-back enable (FBE): Reserved

SERR# Enable (SEE): The PT function never generates an SERR#.

This bit is Reserved.

Wait Cycle Enable (WCC): Reserved

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