 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
82G33 Datasheet(PDF) 335 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82G33 Datasheet(HTML) 335 Page - Intel Corporation |
|
|
335 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 335 Bit Access & Default Description 6 RO 0b Parity Error Response Enable (PEE): No Parity detection in PT functions. This bit is Reserved. 5 RO 0b VGA Palette Snooping Enable (VGA): Reserved 4 RO 0b Memory Write and Invalidate Enable (MWIE): Reserved 3 RO 0b Special Cycle enable (SCE): Reserved 2 RW 0b Bus Master Enable (BME): Controls the KT function's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. For KT, the only bus mastering activity is MSI generation. 0 = Disable 1 = Enable 1 RW 0b Memory Space Enable (MSE): This bit controls Access to the PT function's target memory space. 0 = Disable 1 = Enable 0 RW 0b I/O Space enable (IOSE): This bit controls access to the PT function's target I/O space. 0 = Disable 1 = Enable |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
