82G33 datasheet(331/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

Datasheet

331

9.3.25

MA—Message Signaled Interrupt Message Address

B/D/F/Type:

0/3/2/PCI

Address Offset:

D4–D7h

Default Value:

00000000h

Access:

RO, RW

Size:

32 bits

This register specifies the DWord aligned address programmed by system software for

sending MSI.

Note: Reset: Host system Reset or D3->D0 transition.

Bit

Access &

Default

Description

31:2

00000000h

Address (ADDR): Lower 32 bits of the system specified message

address, always DWORD aligned

Force host MSI address to 0_FEEx_XXXXh before sending to

backbone, regardless of values programmed in MA and MUA registers

under respective PCI Configuration Space. Note that the MA and MUA

registers should continued to be RW (no change to registers

implementation, just hardcode 0_FEEh as bit[35:20] for MSI cycles to

backbone).

1:0

00b

Reserved

9.3.26

MAU—Message Signaled Interrupt Message Upper Address

B/D/F/Type:

0/3/2/PCI

Address Offset:

D8–DBh

Default Value:

00000000h

Access:

RO, RW

Size:

32 bits

This register provides the upper 32 bits of the message address for the 64bit address

capable device.

Note: Reset: Host system Reset or D3->D0 transition.

Bit

Access &

Default

Description

31:4

0000000h

Reserved

3:0

0000b

Address (ADDR): Upper 4 bits of the system specified message

address

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