| Electronic Components Datasheet Search |
|
82G33 Datasheet(PDF) 327 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82G33 Datasheet(HTML) 327 Page - Intel Corporation |
|
327 / 437 page ![]() Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 327 9.3.18 MGNT—Minimum Grant B/D/F/Type: 0/3/2/PCI Address Offset: 3Eh Default Value: 00h Access: RO Size: 8 bits This optional register is not implemented. Bit Access & Default Description 7:0 RO 00h Reserved 9.3.19 MLAT—Maximum Latency B/D/F/Type: 0/3/2/PCI Address Offset: 3Fh Default Value: 00h Access: RO Size: 8 bits This optional register is not implemented. Bit Access & Default Description 7:0 RO 00h Reserved 9.3.20 PID—PCI Power Management Capability ID B/D/F/Type: 0/3/2/PCI Address Offset: C8–C9h Default Value: D001h Access: RO Size: 16 bits See register definitions below Bit Access & Default Description 15:8 RO D0h Next Capability (NEXT): The value of D0h points to the MSI capability. 7:0 RO 01h Cap ID (CID): Indicates that this pointer is a PCI power management. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |