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82G33 Datasheet(PDF) 324 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 324 Page - Intel Corporation

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
324
Datasheet
9.3.13
LBAR—Legacy Bus Master Base Address
B/D/F/Type:
0/3/2/PCI
Address Offset:
20–23h
Default Value:
00000001h
Access:
RO, RW
Size:
32 bits
This Bar is used to allocate I/O space for the SFF-8038i mode of operation (a.k.a. Bus
Master IDE).
Note: Reset: Host system Reset or D3->D0 transition.
Bit
Access &
Default
Description
31:16
RO
0000h
Reserved
15:4
RW
000h
Base Address (BA): This field provides the base address of the I/O
space (16 consecutive I/O locations).
3:1
RO
000b
Reserved
0
RO
1b
Resource Type Indicator (RTE): Indicates a request for I/O space.



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