 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
82G33 Datasheet(PDF) 321 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82G33 Datasheet(HTML) 321 Page - Intel Corporation |
|
|
321 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 321 9.3.7 MLT—Master Latency Timer B/D/F/Type: 0/3/2/PCI Address Offset: 0Dh Default Value: 00h Access: RO Size: 8 bits This register defines the minimum number of PCI clocks the bus master can retain ownership of the bus whenever it initiates new transactions. Bit Access & Default Description 7:0 RO 00h Master Latency Timer (MLT): Not implemented since the function is in (G)MCH. 9.3.8 HTYPE—Header Type B/D/F/Type: 0/3/2/PCI Address Offset: 0Eh Default Value: 00h Access: RO Size: 8 bits Bit Access & Default Description 7:0 RO 00h Reserved |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
