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82G33 Datasheet(PDF) 320 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 320 Page - Intel Corporation

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
320
Datasheet
9.3.4
RID—Revision ID
B/D/F/Type:
0/3/2/PCI
Address Offset:
08h
Default Value:
00h
Access:
RO
Size:
8 bits
This register specifies a device specific revision.
Bit
Access &
Default
Description
7:0
RO
00h
Revision ID (RID): Refer to the Intel® 3 Series Express Chipset
Family Specification Update for the value of the Revision ID register.
9.3.5
CC—Class Codes
B/D/F/Type:
0/3/2/PCI
Address Offset:
09–0Bh
Default Value:
010185h
Access:
RO
Size:
24 bits
This register identifies the basic functionality of the device (i.e., IDE mass storage).
Bit
Access &
Default
Description
23:0
RO
010185h
Programming Interface BCC SCC (PI BCC SCC):
9.3.6
CLS—Cache Line Size
B/D/F/Type:
0/3/2/PCI
Address Offset:
0Ch
Default Value:
00h
Access:
RO
Size:
8 bits
This register defines the system cache line size in DWORD increments. This register is
mandatory for master that use the Memory-Write and Invalidate command.
Bit
Access &
Default
Description
7:0
RO
00h
Cache Line Size (CLS): All writes to system memory are memory
writes.



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