82G33 datasheet(318/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

318

Datasheet

Bit

Access &

Default

Description

15:11

00h

Reserved

Interrupt Disable (ID): This disables pin-based INTx# interrupts.

This bit has no effect on MSI operation.

0 = Enable. Internal INTx# messages are generated if there is an

interrupt and MSI is not enabled.

1 = Disable. Internal INTx# messages will not be generated.

Fast back-to-back enable (FBE): Reserved

SERR# Enable (SEE): The PT function never generates an SERR#.

This bit is reserved.

Wait Cycle Enable (WCC): Reserved

Parity Error Response Enable (PEE): No Parity detection in PT

functions. This bit is reserved.

VGA Palette Snooping Enable (VGA): Reserved

Memory Write and Invalidate Enable (MWIE): Reserved

Special Cycle enable (SCE): Reserved

Bus Master Enable (BME): This bit controls the PT function's ability to

act as a master for data transfers. This bit does not impact the

generation of completions for split transaction commands.

0 = Disable

1 = Enable

Memory Space Enable (MSE): PT function does not contain target

memory space.

I/O Space enable (IOSE): This bit controls access to the PT

function's target I/O space.

0 = Disable

1 = Enable

82G33 Datasheet(PDF) 318 Page - Intel Corporation