82G33 datasheet(319/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

Datasheet

319

9.3.3

STS—Device Status

B/D/F/Type:

0/3/2/PCI

Address Offset:

06–07h

Default Value:

00B0h

Access:

Size:

16 bits

This register is used by the function to reflect its PCI status to the host for the

functionality that it implements.

Bit

Access &

Default

Description

Detected Parity Error (DPE): No parity error on its interface.

Signaled System Error (SSE): The PT function will never generate

an SERR#.

Received Master-Abort Status (RMA): Reserved

Received Target-Abort Status (RTA): Reserved

Signaled Target-Abort Status (STA): The PT Function will never

generate a target abort. This bit is reserved.

10:9

DEVSEL# Timing Status (DEVT): Controls the device select time for

the PT function's PCI interface.

Master Data Parity Error Detected) (DPD): PT function (IDER), as

a master, does not detect a parity error. Other PT function is not a

master and hence this bit is reserved also.

Fast back to back capable (RSVD): Reserved

Reserved

66MHz capable (RSVD):

Capabilities List (CL): This bit indicates that there is a capabilities

pointer implemented in the device.

Interrupt Status (IS): This bit reflects the state of the interrupt in

the function. Setting of the Interrupt Disable bit to 1 has no affect on

this bit. Only when this bit is a 1 and ID bit is 0 is the INTc interrupt

asserted to the Host

2:0

000b

Reserved

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