82G33 datasheet(323/437 Pages) INTEL

323 / 437 page

Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

Datasheet

323

9.3.11

SCMDBA—Secondary Command Block Base Address

B/D/F/Type:

0/3/2/PCI

Address Offset:

18–1Bh

Default Value:

00000001h

Access:

RO, RW

Size:

32 bits

This 8-byte I/O space is used in Native Mode for the secondary Controller's Command

Block. Secondary Channel is not implemented and reads return 7F7F7F7Fh and all

writes are ignored.

Note: Reset: Host System Reset or D3->D0 transition of the function.

Bit

Access &

Default

Description

31:16

0000h

Reserved

15:3

0000h

Base Address (BAR): This field provides the base address of the I/O

space (8 consecutive I/O locations)

2:1

00b

Reserved

Resource Type Indicator (RTE): Indicates a request for I/O space

9.3.12

SCTLBA—Secondary Control Block base Address

B/D/F/Type:

0/3/2/PCI

Address Offset:

1C–1Fh

Default Value:

00000001h

Access:

RO, RW

Size:

32 bits

This 4-byte I/O space is used in Native Mode for Secondary Controller's Control block.

Secondary Channel is not implemented and reads return 7F7F7F7Fh and all writes are

ignored.

Note: Reset: Host System Reset or D3->D0 transition.

Bit

Access &

Default

Description

31:16

0000h

Reserved

15:2

0000h

Base Address (BAR): This field provides the base address of the I/O

space (4 consecutive I/O locations)

Reserved

Resource Type Indicator (RTE): Indicates a request for I/O space

82G33 Datasheet(PDF) 323 Page - Intel Corporation

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