82G33 datasheet(326/437 Pages) INTEL

326 / 437 page

Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

326

Datasheet

9.3.16

CAP—Capabilities Pointer

B/D/F/Type:

0/3/2/PCI

Address Offset:

34h

Default Value:

C8h

Access:

Size:

8 bits

This optional register is used to point to a linked list of new capabilities implemented

by the device.

Bit

Access &

Default

Description

7:0

C8h

Capability Pointer (CP): This field indicates that the first capability

pointer offset is offset C8h ( the power management capability)

9.3.17

INTR—Interrupt Information

B/D/F/Type:

0/3/2/PCI

Address Offset:

3C–3Dh

Default Value:

0300h

Access:

RW, RO

Size:

16 bits

See definitions in the registers below.

Note: Reset: Host System Reset or D3->D0 reset of the function.

Bit

Access &

Default

Description

15:8

03h

Interrupt Pin (IPIN): a value of 0x1/0x2/0x3/0x4 indicates that this

function implements legacy interrupt on INTA/INTB/INTC/INTD,

respectively

Function

Value

INTx

(2 IDE)

03h

INTC

7:0

00h

Interrupt Line (ILINE): The value written in this register indicates

which input of the system interrupt controller, the device's interrupt pin

is connected. This value is used by the OS and the device driver, and

has no affect on the hardware.

82G33 Datasheet(PDF) 326 Page - Intel Corporation

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