82G33 datasheet(330/437 Pages) INTEL

330 / 437 page

Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

330

Datasheet

9.3.23

MID—Message Signaled Interrupt Capability ID

B/D/F/Type:

0/3/2/PCI

Address Offset:

D0–D1h

Default Value:

0005h

Access:

Size:

16 bits

Message Signaled Interrupt is a feature that allows the device/function to generate an

interrupt to the host by performing a DWORD memory write to a system specified

address with system specified data. This register is used to identify and configure an

MSI capable device.

Bit

Access &

Default

Description

15:8

00h

Next Pointer (NEXT): Value indicates this is the last item in the

capabilities list.

7:0

05h

Capability ID (CID): Capabilities ID value indicates device is capable

of generating an MSI.

9.3.24

MC—Message Signaled Interrupt Message Control

B/D/F/Type:

0/3/2/PCI

Address Offset:

D2–D3h

Default Value:

0080h

Access:

RO, RW

Size:

16 bits

This register provides System Software control over MSI.

Note: Reset: Host System Reset or D3->D0 transition.

Bit

Access &

Default

Description

15:8

00h

Reserved

64 Bit Address Capable (C64): Capable of generating 64-bit and 32-

bit messages

6:4

000b

Multiple Message Enable (MME): These bits are R/W for software

compatibility, but only one message is ever sent by the PT function

3:1

000b

Multiple Message Capable (MMC): Only one message is required

MSI Enable (MSIE): If set MSI is enabled and traditional interrupt

pins are not used to generate interrupts

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