82G33 datasheet(314/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

314

Datasheet

9.2.21

MA— Message Signaled Interrupt Message Address

B/D/F/Type:

0/3/1/PCI

Address Offset:

90–93h

Default Value:

00000000h

Access:

RW, RO

Size:

32 bits

Bit

Access &

Default

Description

31:2

00000000h

Address (ADDR): This field provides the lower 32 bits of the system

specified message address, always DWord aligned.

MSI is not translated in Vtd, therefore, in order to avoid sending bad

MSI with address bit [31:20] will be masked internally to generate

12'hFEE regardless of content in register. Register attribute remains

as RW.

1:0

00b

Reserved

9.2.22

MUA— Message Signaled Interrupt Upper Address

(Optional)

B/D/F/Type:

0/3/1/PCI

Address Offset:

94–97h

Default Value:

00000000h

Access:

Size:

32 bits

Bit

Access &

Default

Description

31:0

00000000h

Upper Address (UADDR): Upper 32 bits of the system specified

message address. This register is optional and only implemented if

MC.C64=1.

MSI is not translated in Vtd, therefore, in order to avoid sending bad

MSI with address bit [3:0] will be masked internally to generate 4'h0

regardless of content in register. Register attribute remains as RW.

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