82G33 datasheet(312/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

312

Datasheet

9.2.18

PMCS— PCI Power Management Control And Status

B/D/F/Type:

0/3/1/PCI

Address Offset:

54–55h

Default Value:

0008h

Access:

RO, RW, RWC

Size:

16 bits

Bit

Access &

Default

Description

RWC

PME Status (PMES): The PME Status bit in HECI space can be set to 1

by ME FW performing a write into AUX register to set PMES.

This bit is cleared by host processor writing a 1 to it. ME FW cannot

clear this bit. Host processor writes with value 0 have no effect on this

bit.

This bit is reset to 0 by MRST#.

14:9

000000b

Reserved.

PME Enable (PMEE): This bit is read/write, under control of host

software. It does not directly have an effect on PME events. However,

this bit is shadowed into AUX space so ME FW can monitor it. The ME

FW is responsible for ensuring that FW does not cause the PME-S bit to

transition to 1 while the PMEE bit is 0, indicating that host software had

disabled PME.

This bit is reset to 0 by MRST#.

7:4

0000b

Reserved

No_Soft_Reset (NSR): This bit indicates that when the HECI host

controller is transitioning from D3hot to D0 due to power state

command, it does not perform an internal reset. Configuration context

is preserved: Reserved.

Reserved

1:0

00b

Power State (PS): This field is used both to determine the current

power state of the HECI host controller and to set a new power state.

00 = D0 state

11 = D3HOT state

The D1 and D2 states are not supported for this HECI host controller.

When in the D3HOT state, the configuration space is available, but the

82G33 Datasheet(PDF) 312 Page - Intel Corporation

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