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82G33 Datasheet(PDF) 341 Page - Intel Corporation |
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82G33 Datasheet(HTML) 341 Page - Intel Corporation |
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341 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 341 9.4.12 EROM—Expansion ROM Base Address B/D/F/Type: 0/3/3/PCI Address Offset: 30–33h Default Value: 00000000h Access: RO Size: 32 bits This optional register is not implemented. Bit Access & Default Description 31:11 RO 000000h Expansion ROM Base Address (ERBAR): 10:1 RO 000h Reserved 0 RO 0b Enable (EN): Enable expansion ROM Access 9.4.13 CAP—Capabilities Pointer B/D/F/Type: 0/3/3/PCI Address Offset: 34h Default Value: C8h Access: RO Size: 8 bits This optional register is used to point to a linked list of new capabilities implemented by the device. Bit Access & Default Description 7:0 RO C8h Capability Pointer (CP): This field indicates that the first capability pointer offset is offset c8h ( the power management capability) |
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