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82G33 Datasheet(PDF) 344 Page - Intel Corporation |
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82G33 Datasheet(HTML) 344 Page - Intel Corporation |
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344 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 344 Datasheet 9.4.18 PC—PCI Power Management Capabilities B/D/F/Type: 0/3/3/PCI Address Offset: CA–CBh Default Value: 0023h Access: RO Size: 16 bits This register implements the power management capabilities of the function. Bit Access & Default Description 15:11 RO 00000b PME Support (PME): Indicates no PME# in the PT function. 10 RO 0b D2 Support (D2S): The D2 state is not Supported. 9 RO 0b D1 Support (D1S): The D1 state is not supported. 8:6 RO 000b Aux Current (AUXC): PME# from D3 (cold) state is not supported; therefore, this field is 000b. 5 RO 1b Device Specific Initialization (DSI): Indicates that no device- specific initialization is required. 4 RO 0b Reserved 3 RO 0b PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#. 2:0 RO 011b Version (VS): Indicates support for revision 1.2 of the PCI power management specification. |
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