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82G33 Datasheet(PDF) 347 Page - Intel Corporation |
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82G33 Datasheet(HTML) 347 Page - Intel Corporation |
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347 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 347 9.4.21 MC—Message Signaled Interrupt Message Control B/D/F/Type: 0/3/3/PCI Address Offset: D2–D3h Default Value: 0080h Access: RO, RW Size: 16 bits This register provides System Software control over MSI. Note: Reset: Host System Reset or D3->D0 transition. Bit Access & Default Description 15:8 RO 00h Reserved 7 RO 1b 64 Bit Address Capable (C64): Capable of generating 64-bit and 32- bit messages. 6:4 RW 000b Multiple Message Enable (MME): These bits are R/W for software compatibility, but only one message is ever sent by the PT function. 3:1 RO 000b Multiple Message Capable (MMC): Only one message is required. 0 RW 0b MSI Enable (MSIE): 0 = Disable. 1 = Enable. Traditional interrupt pins are not used to generate interrupts. |
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