82G33 datasheet(350/437 Pages) INTEL

350 / 437 page

Functional Description

350

Datasheet

Functional Description

10.1

Host Interface

The (G)MCH supports the Intel® Core™2 Duo desktop processor subset of the

Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous

transfer is used for the address and data signals. The address signals are double

pumped and a new address can be generated every other bus clock. At 200/267/333

MHz bus clock the address signals run at 667 MT/s. The data is quad pumped and an

entire 64B cache line can be transferred in two bus clocks. At 200/266/333 MHz bus

clock, the data signals run at 800/1066/1333 MT/s for a maximum bandwidth of

6.4/8.5/10.6 GB/s.

10.1.1

FSB IOQ Depth

The Scalable Bus supports up to 12 simultaneous outstanding transactions.

10.1.2

FSB OOQ Depth

The (G)MCH supports only one outstanding deferred transaction on the FSB.

10.1.3

FSB GTL+ Termination

The (G)MCH integrates GTL+ termination resistors on die.

10.1.4

FSB Dynamic Bus Inversion

The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving

data from the processor. DBI limits the number of data signals that are driven to a low

voltage on each quad pumped data phase. This decreases the worst-case power

consumption of the (G)MCH. FSB_DINVB_3:0 indicate if the corresponding 16 bits of

data are inverted on the bus for each quad pumped data phase.

FSB_DINVB_3:0

Data Bits

FSB_DINVB_0

FSB_DB_15:0

FSB_DINVB_1

FSB_DB_31:16

FSB_DINVB_2

FSB_DB_47:32

FSB_DINVB_3

FSB_DB_63:48

82G33 Datasheet(PDF) 350 Page - Intel Corporation