82G33 datasheet(352/437 Pages) INTEL

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Functional Description

352

Datasheet

10.2

System Memory Controller

The 82G33 GMCH and 82P35 MCH system memory controllers support both DDR2 and

DDR3 protocols with two independent 64 bit wide channels; each accessing one or two

DIMMs. The (G)MCH supports a maximum of two un-buffered, non-ECC DDR2 or

DDR3 DIMMs per channel; thus, allowing up to four device ranks per channel. The

82Q35 GMCH and 82Q33 GMCH only support DDR2.

Note: References in this section to DDR3 are for the 82G33 GMCH and 82P35 only.

10.2.1

System Memory Organization Modes

The system memory controller supports three memory organization modes, Single

Channel, Dual Channel Symmetric, and Dual Channel Asymmetric.

10.2.2

Single Channel Mode

In this mode, all memory cycles are directed to a single channel. Single channel mode

is used when either Channel A or Channel B DIMMs are populated in any order, but

not both.

10.2.3

Dual Channel Symmetric Mode

This mode provides maximum performance on real applications. Addresses are ping-

ponged between the channels after each cache line (64 byte boundary). If there are

two requests, and the second request is to an address on the opposite channel from

the first, that request can be sent before data from the first request has returned. If

two consecutive cache lines are requested, both may be retrieved simultaneously,

since they are ensured to be on opposite channels.

Dual channel symmetric mode is used when both Channel A and Channel B DIMMs are

populated in any order with the total amount of memory in each channel being the

same, but the DRAM device technology and width may vary from one channel to the

other.

Table 10-1 is a sample dual channel symmetric memory configuration showing the

rank organization.

82G33 Datasheet(PDF) 352 Page - Intel Corporation