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82G33 Datasheet(PDF) 346 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 346 Page - Intel Corporation

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
346
Datasheet
Bit
Access &
Default
Description
1:0
RW
00b
Power State (PS): This field is used both to determine the current
power state of the PT function and to set a new power state.
00 = D0 state
11 = D3HOT state
When in the D3HOT state, the controller's configuration space is
available, but the I/O and memory spaces are not. Additionally,
interrupts are blocked. If software attempts to write a 10 or 01 to
these bits, the write will be ignored.
9.4.20
MID—Message Signaled Interrupt Capability ID
B/D/F/Type:
0/3/3/PCI
Address Offset:
D0–D1h
Default Value:
0005h
Access:
RO
Size:
16 bits
Message Signaled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a DWORD memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
Bit
Access &
Default
Description
15:8
RO
00h
Next Pointer (NEXT): Value indicates this is the last item in the list.
7:0
RO
05h
Capability ID (CID): value of Capabilities ID indicates device is
capable of generating MSI.



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