82G33 datasheet(345/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

Datasheet

345

9.4.19

PMCS—PCI Power Management Control and Status

B/D/F/Type:

0/3/3/PCI

Address Offset:

CC–CFh

Default Value:

00000000h

Access:

RO/V, RO, RW

Size:

32 bits

BIOS Optimal Default

0000h

This register implements the PCI PM Control and Status Register to allow PM state

transitions and Wake up.

Note: Note the NSR bit of this register. All registers (PCI configuration and Device Specific)

marked with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a

1, the D3->D0 transition will not reset the registers.

Note: Reset: Host System Reset or D3->D0 transition.

Bit

Access &

Default

Description

31:16

Reserved

PME Status (PMES): This bit is set when a PME event is to be

requested. Not supported

14:9

00h

Reserved

PME Enable (PMEE): Not Supported

7:4

Reserved

RO/V

No Soft Reset (NSR):

1 = Indicates that devices transitioning from D3hot to D0 because of

PowerState commands do not perform an internal reset.

Configuration Context is preserved. Upon transition from the

D3hot to the D0 Initialized state, no additional operating system

intervention is required to preserve Configuration Context beyond

writing the PowerState bits.

0 = Devices do perform an internal reset upon transitioning from

D3hot to D0 via software control of the PowerState bits.

Configuration Context is lost when performing the soft reset. Upon

transition from the D3hot to the D0 state, full re-initialization

sequence is needed to return the device to D0 Initialized.

When this bit is 0, device performs internal reset.

When this bit is 1, device does not perform internal reset.

Reserved

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