82G33 datasheet(342/437 Pages) INTEL

342 / 437 page

Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

342

Datasheet

9.4.14

INTR—Interrupt Information

B/D/F/Type:

0/3/3/PCI

Address Offset:

3C–3Dh

Default Value:

0200h

Access:

RW, RO

Size:

16 bits

See individual Registers below.

Note: Reset: Host System Reset or D3->D0 reset of the function.

Bit

Access &

Default

Description

15:8

02h

Interrupt Pin (IPIN): a value of 0x1/0x2/0x3/0x4 indicates that this

function implements legacy interrupt on INTA/INTB/INTC/INTD,

respectively

Function

Value

INTx

( 3 KT/Serial Port)

02h

INTB

7:0

00h

Interrupt Line (ILINE): The value written in this field indicates which

input of the system interrupt controller, the device's interrupt pin is

connected to. This value is used by the OS and the device driver, and

has no affect on the hardware.

9.4.15

MGNT—Minimum Grant

B/D/F/Type:

0/3/3/PCI

Address Offset:

3Eh

Default Value:

00h

Access:

Size:

8 bits

This optional register is not implemented.

Bit

Access &

Default

Description

7:0

00h

Reserved

82G33 Datasheet(PDF) 342 Page - Intel Corporation

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