G35 datasheet(67/351 Pages) INTEL

67 / 351 page

GMCH Register Description

Datasheet

4.1

The following table shows the register-related terminology that is used.

Item

Description

Read Only bit(s). Writes to these bits have no effect.

RS/WC

Read Set / Write Clear bit(s). These bits are set to ‘1’ when read and then will

continue to remain set until written. A write of ‘1’ clears (sets to ‘0’) the

corresponding bit(s) and a write of ‘0’ has no effect.

R/W

Read / Write bit(s). These bits can be read and written.

R/WC

Read / Write Clear bit(s). These bits can be read. Internal events may set this

bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’

has no effect.

R/WC/S

Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may

set this bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write

of ‘0’ has no effect. Bits are not cleared by "warm" reset, but will be reset with a

cold/complete reset (for PCI Express* related bits a cold reset is “Power Good

Reset” as defined in the PCI Express* Specification).

R/W/K

Read / Write / Key bit(s). These bits can be read and written by software.

Additionally this bit when set, prohibits some other bit field(s) from being

writeable (bit fields become Read Only).

R/W/L

Read / Write / Lockable bit(s). These bits can be read and written. Additionally

there is a bit (which may or may not be a bit marked R/W/L) that, when set,

prohibits this bit field from being writeable (bit field becomes Read Only).

R/W/S

Read / Write / Sticky bit(s). These bits can be read and written. Bits are not

cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI

Express related bits a cold reset is “Power Good Reset” as defined in the PCI

Express* Specification).

R/WSC

Read / Write Self Clear bit(s). These bits can be read and written. When the bit

is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly

sooner than any subsequent read could retrieve a ‘1’.

R/WSC/L

Read / Write Self Clear / Lockable bit(s). These bits can be read and written.

When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events,

possibly sooner than any subsequent read could retrieve a ‘1’. Additionally there

is a bit (which may or may not be a bit marked R/W/L) that, when set, prohibits

this bit field from being writeable (bit field becomes Read Only).

R/WO

Write Once bit(s). Once written, bits with this attribute become Read Only.

These bits can only be cleared by a Reset.

Write Only. Whose bits may be written, but will always-return zeros when read.

They are used for write side effects. Any data written to these registers cannot

be retrieved.

G35 Datasheet(PDF) 67 Page - Intel Corporation

G35 Datasheet(HTML) 67 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL