G35 datasheet(79/351 Pages) INTEL

79 / 351 page

DRAM Controller Registers (D0:F0)

Datasheet

Address

Offset

Symbol

Default

Value

Access

60–67h

PCIEXBAR

PCI Express Register Range Base

Address

00000000E0

000000h

RO, RW,

RW/L,

RW/K

68–6Fh

DMIBAR

Root Complex Register Range

Base Address

0000000000

000000h

RO, RW

90h

PAM0

Programmable Attribute Map 0

00h

RO, RW

91h

PAM1

Programmable Attribute Map 1

00h

RO, RW

92h

PAM2

Programmable Attribute Map 2

00h

RO, RW

93h

PAM3

Programmable Attribute Map 3

00h

RO, RW

94h

PAM4

Programmable Attribute Map 4

00h

RO, RW

95h

PAM5

Programmable Attribute Map 5

00h

RO, RW

96h

PAM6

Programmable Attribute Map 6

00h

RO, RW

97h

LAC

Legacy Access Control

00h

RO, RW

98–99h

REMAPBASE

Remap Base Address Register

03FFh

RO, RW

9A–9Bh

REMAPLIMI

Remap Limit Address Register

0000h

RO, RW

9Dh

SMRAM

System Management RAM Control

02h

RO, RW/L,

RW,

RW/L/K

9Eh

ESMRAMC

Extended System Management

RAM Control

38h

RW/L,

RWC, RO

A0–A1h

TOM

Top of Memory

0001h

RO, RW/L

A2–A3h

TOUUD

Top of Upper Usable Dram

0000h

RW/L

A4–A7h

GBSM

Graphics Base of Stolen Memory

00000000h

RW/L ,RO

AC–AFh

TSEGMB

TSEG Memory Base

00000000h

RW/L, RO

B0–B1h

TOLUD

Top of Low Usable DRAM

0010h

RW/L RO

C8–C9h

ERRSTS

Error Status

0000h

RO,

RWC/S

CA–CBh

ERRCMD

Error Command

0000h

RO, RW

CC–CDh

SMICMD

SMI Command

0000h

RO, RW

DC–DFh

SKPD

Scratchpad Data

00000000h

E0–E9h

CAPID0

Capability Identifier

0000000000

0001090009

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