G35 datasheet(27/351 Pages) INTEL

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Introduction

Datasheet

Capabilities of the SDVO and Analog Display interfaces include:

•

SDVO Support

⎯

SDVO ports in either single modes supported

⎯

3x3 Built In full panel scalar

⎯

180 degree Hardware screen rotation

⎯

Multiplexed Digital Display Channels (Supported with ADD2/MEC)

⎯

Two channels multiplexed with PCI Express* Graphics port

⎯

270 MHz dot clock on each 12-bit interface

⎯

Supports flat panels up to 2048 x 1536 @ 60 Hz or digital CRT/HDTV at

1920 x1080 @ 85 Hz

⎯

Supports Hot-Plug and Display

⎯

Supports TMDS transmitters or TV-out encoders

⎯

ADD2/Media Expansion card utilizes PCI Express Graphics x16 connector

•

Analog Display Support

⎯

400 MHz Integrated 24-bit RAMDAC

⎯

Up to 2048x1536 @ 75 Hz refresh

⎯

Hardware Color Cursor Support

⎯

DDC2B Compliant Interface

•

Dual Independent Display options with digital display

1.3.7

GMCH Clocking

•

Differential Host clock of 200/266/333 MHz (HCLKP/HCLKN). These frequencies

Support transfer rates of 800/1066/1333 MT/s. The Host PLL generates 2x, 4x,

and 8x versions of the host clock for internal optimizations.

•

Chipset core clock synchronized to host clock

•

Internal and External Memory clocks of 266, 333 and 400 MHz generated from

one of two GMCH PLLs that use the Host clock as a reference. Includes 2x and 4x

for internal optimizations.

•

The PCI Express* PLL of 100 MHz Serial Reference Clock (GCLKP/GCLKN)

generates the PCI Express core clock of 250 MHz

•

Display timings are generated from display PLLs that use a 96 MHz differential

non-spread spectrum clock as a reference. Display PLLs can also use the

SDVO_TVCLKIN[+/-] from an SDVO device as a reference.

•

All of the above clocks are capable of tolerating Spread Spectrum clocking as

defined in the Clock Generator specification.

•

Host, Memory, and PCI Express Graphics PLLs and all associated internal clocks

are disabled until PWROK is asserted.

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