G35 datasheet(71/351 Pages) INTEL

71 / 351 page

GMCH Register Description

Datasheet

Just the same as with PCI devices, each device is selected based on decoded address

information that is provided as a part of the address portion of Configuration Request

packets. A PCI Express device will decode all address information fields (bus, device,

function and extended address numbers) to provide access to the correct register.

To access this space (steps 1, 2, 3 are done only once by BIOS),

1. use the PCI compatible configuration mechanism to enable the PCI Express

enhanced configuration mechanism by writing 1 to bit 0 of the PCI

EXPRESS*XBAR register.

2. use the PCI compatible configuration mechanism to write an appropriate PCI

Express base address into the PCI EXPRESS*XBAR register

3. calculate the host address of the register you wish to set using (PCI Express

base + (bus number * 1 MB) + (device number * 32KB) + (function number *

4 KB) + (1 B * offset within the function) = host address)

4. use a memory write or memory read cycle to the calculated host address to

write or read that register.

4.4

Routing Configuration Accesses

The GMCH supports two PCI related interfaces: DMI and PCI Express. The GMCH is

responsible for routing PCI and PCI Express configuration cycles to the appropriate

device that is an integrated part of the GMCH or to one of these two interfaces.

Configuration cycles to the ICH8 internal devices and Primary PCI (including

downstream devices) are routed to the ICH8 via DMI. Configuration cycles to both the

PCI Express Graphics PCI compatibility configuration space and the PCI Express

Graphics extended configuration space are routed to the PCI Express Graphics port

device or associated link.

G35 Datasheet(PDF) 71 Page - Intel Corporation