G35 datasheet(23/351 Pages) INTEL

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Introduction

Datasheet

1.3

GMCH Overview

The 82G35 Graphics and Memory Controller Hub (GMCH) is designed for use with the

Intel® CoreTM2 Duo processors and Intel® CoreTM2 Quad processors in desktop

platforms. The role of a GMCH in a system is to manage the flow of information

between its four interfaces: the processor interface (FSB), the System Memory

interface (DRAM controller), the External Graphics interface, and the I/O Controller

through DMI interface. This includes arbitrating between the four interfaces when each

initiates transactions. The GMCH is optimized for the Intel® CoreTM2 Duo processor

and Intel® CoreTM2 Quad processor in an LGA775 socket. It supports one or two

channels of DDR2 SDRAM. It also supports the PCI Express* based external graphics

attach. The G35 chipset platform supports the eighth generation I/O Controller Hub

(Intel ICH8) to provide a multitude of I/O related features.

1.3.1

Host Interface

The GMCH can use a single LGA775 socket processor. The GMCH supports a FSB

frequencies of 800/1066/1333 MHz using a scalable FSB Vcc_CPU. It supports 36-bit

host addressing, decoding up to 8 GB of the processor’s memory address space. Host-

initiated I/O cycles are decoded to PCI Express, DMI, or the GMCH configuration

space. Host-initiated memory cycles are decoded to PCI Express, DMI or system DDR.

PCI Express device accesses to non-cacheable system memory are not snooped on the

host bus. Memory accesses initiated from PCI Express using PCI semantics and from

DMI to system SDRAM will be snooped on the host bus.

Processor/Host Interface (FSB) Details

•

Supports a single Intel® CoreTM2 Duo processors and Intel® CoreTM2 Quad

processors

•

Supports Front Side Bus (FSB) at 800/1066/1333 MT/s (200/266/333 MHz)

•

Supports FSB Dynamic Bus Inversion (DBI)

•

Supports 36-bit host bus addressing, allowing the processor to access the entire

64 GB of the host address space.

•

Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined

address requests on the host bus

•

Has a 1-deep Defer Queue

•

Uses GTL+ bus driver with integrated GTL termination resistors

•

Supports a Cache Line Size of 64 bytes

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