G35 datasheet(51/351 Pages) INTEL

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System Address Map

Datasheet

Figure 3-3. Main Memory Address Range

Main Memory

ISA Hole (optional)

DOS Compatibility Memory

FLASH

FFFF_FFFFh

00F0_0000h

15MB

16MB

0100_0000h

0MB

TOLUD

APIC

Main Memory

0010_0000h

1MB

IGD (1-64MB, optional)

TSEG (1MB/2MB/8MB, optional)

PCI Memory Range

4GB Max

Contains:

Dev 0, 1, 2, 3, 7

BARS

& ICH/PCI ranges

3.2.1

ISA Hole (15MB-16MB)

A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable in Device

0 space. Accesses within this hole are forwarded to the DMI Interface. The range of

physical DRAM memory disabled by opening the hole is not remapped to the top of the

memory – that physical DRAM space is not accessible. This 15 MB – 16 MB hole is an

optionally enabled ISA hole.

Video accelerators originally used this hole. It is also used by validation and customer

SV teams for some of their test cards. That is why it is being supported. There is no

inherent BIOS request for the 15 MB – 16 MB window.

3.2.2

TSEG

TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,

which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor

accesses to enabled TSEG access the physical DRAM at the same address. Non-

processor originated accesses are not allowed to SMM space. PCI-Express, DMI, and

Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle

type with reads and writes to location 0 and byte enables turned off for writes. When

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