G35 datasheet(25/351 Pages) INTEL

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Introduction

Datasheet

1.3.3

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the GMCH and

ICH8. This high-speed interface integrates advanced priority-based servicing allowing

for concurrent traffic and true isochronous transfer capabilities. Base functionality is

completely software transparent permitting current and legacy software to operate

normally.

To provide for true isochronous transfers and configurable Quality of Service (QoS)

transactions, the ICH8 supports two virtual channels on DMI: VC0 and VC1. These two

channels provide a fixed arbitration scheme where VC1 is always the highest priority.

VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be

specifically enabled and configured at both ends of the DMI link (i.e., the ICH8 and

GMCH).

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A chip-to-chip connection interface to Intel ICH8

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2 GB/s point-to-point DMI to ICH8 (1 GB/s each direction)

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100 MHz reference clock (shared with PCI Express* Graphics Attach)

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32-bit downstream addressing

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APIC and MSI interrupt messaging support. Will send Intel-defined “End Of

Interrupt” broadcast message when initiated by the processor.

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Message Signaled Interrupt (MSI) messages

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SMI, SCI and SERR error indication

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Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port

DMA, floppy drive, and LPC bus masters

1.3.4

PCI Express* Interface

The GMCH contains one 16-lane (x16) PCI Express port intended for an external PCI

Express graphics card. The PCI Express port is compliant to the PCI Express* Base

Specification revision 1.1. The x16 port operates at a frequency of 2.5 Gb/s on each

lane while employing 8b/10b encoding, and supports a maximum theoretical

bandwidth of 40 Gb/s in each direction.

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One, 16-lane PCI Express port intended for Graphics Attach, compatible to the PCI

Express* Base Specification revision 1.1.

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PCI Express frequency of 1.25GHz resulting in 2.5 Gb/s each direction

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Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of

250 MB/s given the 8b/10b encoding used to transmit data across this interface

•

Maximum theoretical realized bandwidth on the interface of 4 GB/s in each

direction simultaneously, for an aggregate of 8 GB/s when x16.

•

PCI Express* Graphics Extended Configuration Space. The first 256 bytes of

configuration space alias directly to the PCI Compatibility configuration space. The

remaining portion of the fixed 4-KB block of memory-mapped space above that

(starting at 100h) is known as extended configuration space.

•

PCI Express Enhanced Addressing Mechanism. Accessing the device configuration

space in a flat memory mapped fashion.

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