G35 datasheet(3/351 Pages) INTEL

3 / 351 page

Datasheet

Contents

Introduction ...................................................................................................18

1.1

Terminology ........................................................................................20

1.2

Reference Documents ...........................................................................22

1.3

GMCH Overview ...................................................................................23

1.3.1

Host Interface.........................................................................23

1.3.2

System Memory Interface.........................................................24

1.3.3

Direct Media Interface (DMI).....................................................25

1.3.4

PCI Express* Interface.............................................................25

1.3.5

Graphics Features ...................................................................26

1.3.6

SDVO and Analog Display Features ............................................26

1.3.7

GMCH Clocking .......................................................................27

1.3.8

Power Management .................................................................28

1.3.9

Thermal Sensor ......................................................................28

Signal Description ...........................................................................................30

2.1

Host Interface Signals...........................................................................31

2.2

DDR2 DRAM Channel A Interface ............................................................34

2.3

DDR2 DRAM Channel B Interface ............................................................35

2.4

DDR2 DRAM Reference and Compensation ...............................................36

2.5

PCI Express* Interface Signals ...............................................................36

2.6

Analog Display Signals ..........................................................................36

2.7

Clocks, Reset, and Miscellaneous ............................................................37

2.8

Direct Media Interface (DMI)..................................................................38

2.9

Controller Link (CL) ..............................................................................39

2.10

Intel® Serial DVO (SDVO) Interface ........................................................39

2.10.1

SDVO/PCI Express* Signal Mapping ...........................................41

2.11

Power, Ground.....................................................................................42

System Address Map .......................................................................................44

3.1

Legacy Address Range ..........................................................................46

3.1.1

DOS Range (0h – 9_FFFFh).......................................................48

3.1.2

Legacy Video Area (A_0000h–B_FFFFh) ......................................48

3.1.3

Expansion Area (C_0000h–D_FFFFh)..........................................48

3.1.4

Extended System BIOS Area (E_0000h-E_FFFFh).........................49

3.1.5

System BIOS Area (F_0000h – F_FFFFh) ....................................49

3.1.6

PAM Memory Area Details.........................................................50

3.1.7

Legacy Interrupt Routing..........................................................50

3.2

Main Memory Address Range (1MB – TOLUD) ...........................................50

3.2.1

ISA Hole (15MB-16MB) ............................................................51

3.2.2

TSEG.....................................................................................51

3.2.3

Pre-allocated Memory ..............................................................52

3.3

PCI Memory Address Range (TOLUD – 4GB) .............................................52

3.3.1

APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................54

3.3.2

HSEG (FEDA_0000h–FEDB_FFFFh).............................................54

3.3.3

FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFFh) ...............54

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