G35 datasheet(9/351 Pages) INTEL

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Datasheet

8.2.25

PMCAPID—Mirror of Fun 0 Power Management Capabilities ID...... 263

8.2.26

PMCAP—Mirror of Fun 0 Power Management Capabilities ............. 264

8.2.27

PMCS—Power Management Control/Status................................ 265

8.2.28

SWSMI—Mirror of Func0 Software SMI ..................................... 266

Manageability Engine (ME) Registers (D3:F0)................................................... 268

9.1

Host Embedded Controller Interface (HECI1) Configuration

9.1.1

ID—Identifiers ...................................................................... 269

9.1.2

CMD—Command ................................................................... 269

9.1.3

STS—Device Status ............................................................... 271

9.1.4

RID—Revision ID................................................................... 272

9.1.5

CC—Class Code..................................................................... 272

9.1.6

CLS—Cache Line Size............................................................. 272

9.1.7

MLT—Master Latency Timer .................................................... 273

9.1.8

HTYPE—Header Type ............................................................. 273

9.1.9

HECI_MBAR—HECI MMIO Base Address .................................... 274

9.1.10

SS—Sub System Identifiers .................................................... 274

9.1.11

CAP—Capabilities Pointer........................................................ 275

9.1.12

INTR—Interrupt Information ................................................... 275

9.1.13

MGNT—Minimum Grant .......................................................... 275

9.1.14

MLAT—Maximum Latency ....................................................... 276

9.1.15

HFS—Host Firmware Status .................................................... 276

9.1.16

PID—PCI Power Management Capability ID ............................... 276

9.1.17

PC—PCI Power Management Capabilities................................... 277

9.1.18

PMCS—PCI Power Management Control And Status .................... 278

9.1.19

MID—Message Signaled Interrupt Identifiers ............................. 279

9.1.20

MC—Message Signaled Interrupt Message Control ...................... 279

9.1.21

MA—Message Signaled Interrupt Message Address ..................... 280

9.1.22

MD—Message Signaled Interrupt Message Data ......................... 280

9.1.23

HIDM—HECI Interrupt Delivery Mode ....................................... 281

Functional Description ................................................................................... 282

10.1

Host Interface.................................................................................... 282

10.1.1

FSB IOQ Depth ..................................................................... 282

10.1.2

FSB OOQ Depth .................................................................... 282

10.1.3

FSB GTL+ Termination ........................................................... 282

10.1.4

FSB Dynamic Bus Inversion .................................................... 283

10.1.5

APIC Cluster Mode Support ..................................................... 283

10.2

System Memory Controller................................................................... 284

10.2.1

Memory Organization Modes ................................................... 284

10.2.2

DRAM Technologies and Organization ....................................... 286

10.2.3

Main Memory DRAM Address Translation and Decoding ............... 288

10.2.4

DRAM Clock Generation.......................................................... 291

10.2.5

Suspend to RAM and Resume.................................................. 291

10.2.6

DDR2 On-Die Termination ...................................................... 291

10.3

PCI Express* ..................................................................................... 291

10.3.1

PCI Express* Architecture....................................................... 291

10.3.2

Intel® Serial Digital Video Output (SDVO) ................................. 292

10.4

Integrated Graphics Controller ............................................................. 296

10.4.1

Integrated Graphics Device Overview ....................................... 296

10.5

Display Interfaces .............................................................................. 297

10.5.1

Analog Display Port Characteristics .......................................... 299

10.5.2

Digital Display Interface ......................................................... 300

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