G35 datasheet(37/351 Pages) INTEL

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Signal Description

Datasheet

Signal Name

Type

Description

GREEN

GREEN Analog Video Output: This signal is a CRT Analog

video output from the internal color palette DAC. The DAC is

designed for a 37.5 ohm routing impedance, but the terminating

resistor to ground will be 75 ohms (e.g., 75 ohm resistor on the

board, in parallel with a 75 ohm CRT load).

GREEN#

GREEN# Analog Output: This signal is an analog video output

from the internal color palette DAC. It should be shorted to the

ground plane.

BLUE

BLUE Analog Video Output: This signal is a CRT Analog video

output from the internal color palette DAC. The DAC is designed

for a 37.5 ohm routing impedance, but the terminating resistor

to ground will be 75 ohms (e.g., 75 ohm resistor on the board,

in parallel with a 75 ohm CRT load).

BLUE#

BLUE# Analog Output: This signal is an analog video output

from the internal color palette DAC. It should be shorted to the

ground plane.

REFSET

Resistor Set: Set point resistor for the internal color palette

DAC. A 255 ohm 1% resistor is required between REFSET and

motherboard ground.

HSYNC

3.3V

CMOS

CRT Horizontal Synchronization: This signal is used as the

horizontal sync (polarity is programmable) or “sync interval”, 3.3

V output

VSYNC

3.3V

CMOS

CRT Vertical Synchronization: This signal is used as the

vertical sync (polarity is programmable) 3.3V output.

DDC_CLK

I/O

3.3V

CMOS

Monitor Control Clock

DDC_DATA

I/O

3.3V

CMOS

Monitor Control Data

2.7

Clocks, Reset, and Miscellaneous

Signal Name

Type

Description

HCLKP

HCLKN

HCSL

Differential Host Clock In: These pins receive a differential

host clock from the external clock synthesizer. This clock is

used by all of the GMCH logic that is in the Host clock domain.

Memory domain clocks are also derived from this source.

GCLKP

GCLKN

HCSL

Differential PCI Express* Graphics Clock In: These pins

receive a differential 100 MHz Serial Reference clock from the

external clock synthesizer. This clock is used to generate the

clocks necessary for the support of PCI Express.

DREFCLKN

DREFCLKP

HCSL

Display PLL Differential Clock In

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