G35 datasheet(89/351 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

5.1.15

DEVEN—Device Enable

B/D/F/Type:

0/0/0/PCI

Address Offset:

54–57h

Default Value:

000003DBh

Access:

RO, RW/L

Size:

32 bits

This register allows for enabling/disabling of PCI devices and functions that are within

the GMCH.

Bit

Access &

Default

Description

31:10

00000h

Reserved

RW/L

ME Function 3 (D3F3EN):

0 = Bus 0 Device 3 Function 3 is disabled and hidden

1 = Bus 0 Device 3 Function 3 is enabled and visible

If Device 3, Function 0 is disabled and hidden, then Device 3, Function

3 is also disabled and hidden independent of the state of this bit.

RW/L

ME Function 2 (D3F2EN):

0 = Bus 0 Device 3 Function 2 is disabled and hidden

1 = Bus 0 Device 3 Function 2 is enabled and visible

If Device 3, Function 0 is disabled and hidden, then Device 3, Function

2 is also disabled and hidden independent of the state of this bit.

Reserved

RW/L

ME Function 0 (D3F0EN):

0 = Bus 0, Device 3, Function 0 is disabled and hidden

1 = Bus 0, Device 3, Function 0 is enabled and visible.

If this GMCH does not have ME capability (CAPID0[57] = 1), then

Device 3, Function 0 is disabled and hidden independent of the state of

this bit.

Reserved

RW/L

Internal Graphics Engine Function 1 (D2F1EN):

0 = Bus 0, Device 2, Function 1 is disabled and hidden

1 = Bus 0, Device 2, Function 1 is enabled and visible

If Device 2, Function 0 is disabled and hidden, then Device 2, Function

1 is also disabled and hidden independent of the state of this bit.

RW/L

Internal Graphics Engine Function 0 (D2F0EN):

0 = Bus 0, Device 2, Function 0 is disabled and hidden

1 = Bus 0, Device 2, Function 0 is enabled and visible

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