G35 datasheet(38/351 Pages) INTEL

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Signal Description

Datasheet

Signal Name

Type

Description

RSTIN#

HVIN

Reset In: When asserted, this signal will asynchronously reset

the GMCH logic. This signal is connected to the PCIRST#

output of the Intel® ICH8. All PCI Express Graphics Attach

output signals will also tri-state compliant to PCI Express*

Specification Rev 1.1.

This input should have a Schmitt trigger to avoid spurious

resets.

This signal is required to be 3.3V tolerant.

PWROK

HVIN

Power OK: When asserted, PWROK is an indication to the

GMCH that core power has been stable for at least 10us.

EXP_EN

CMOS

PCI Express* SDVO Concurrent Select

0 = Only SDVO or PCI Express Operational

1 = SDVO and PCI Express operating simultaneously via PCI

Express* Graphics port

EXP_SLR

CMOS

PCI Express* Static Lane Reversal/Form Factor

Selection: GMCH’s PCI Express lane numbers are reversed to

differentiate BTX or ATX form factors.

0 = GMCH’s PCI Express lane numbers are reversed (BTX

Platforms)

1 = Normal operation (ATX Platforms)

ICH_SYNC#

HVCMO

ICH Sync: See Design Guide for Implementation.

TEST[2:0]

I/O

In Circuit Test: These pins should be connected to test points

on the mother board. They are internally shorted to the

package ground and can be used to determine if the corner

balls on the GMCH are correctly soldered down to the

motherboard. These pins should NOT connect to ground on the

motherboard. If TEST[2:0] are not going to be used they

should be left as no connects

2.8

Direct Media Interface (DMI)

Signal Name

Type

Description

DMI_RXP[3:0]

DMI_RXN[3:0]

DMI

Direct Media Interface: Receive differential pair (Rx)

DMI_TXP[3:0]

DMI_TXN[3:0]

DMI

Direct Media Interface: Transmit differential pair (Tx)

G35 Datasheet(PDF) 38 Page - Intel Corporation

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