G35 datasheet(24/351 Pages) INTEL

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Introduction

Datasheet

1.3.2

System Memory Interface

The GMCH integrates a system memory DDR2 controller with two, 64-bit wide

interfaces. Only Double Data Rate (DDR2) memory is supported; consequently, the

buffers support only SSTL_1.8 V signal interfaces. The memory controller interface is

fully configurable through a set of control registers.

System Memory Interface Details

•

The GMCH System Memory Controller directly supports one or two channels of

memory (each channel consisting of 64 data lines)

⎯

The memory channels are asymmetric: "Flex Memory" channels are assigned

addresses serially. Channel B addresses are assigned after all Channel A

addresses

⎯

The memory channels are interleaved: Addresses are ping-ponged between

the channels after each cache line (64-B boundary)

•

Supports DDR2 memory DIMM frequencies of 533, 667 and 800 MHz. The speed

used in all channels is the speed of the slowest DIMM in the system

•

I/O Voltage of 1.8 V for DDR2

•

Supports only unbuffered DIMMs

•

Supports maximum memory bandwidth of 6.4 GB/s in single-channel or dual-

channel asymmetric mode, or 12.8 GB/s in dual-channel interleaved mode

assuming DDR2 800MHz

•

Supports 256-Mb, 512-Mb, and 1-Gb technologies for x8 and x16 devices

•

Supports four banks for all DDR2 devices up to 512-Mbit density. Supports eight

banks for 1-Gbit DDR2 devices

•

Using 256 Mb technologies, the smallest memory capacity possible is 128 MB,

assuming Single-Channel Mode. (8 K rows * 512 columns * 1 cell/(row * column)

* 16 b/cell * 4 banks/devices * 4 devices/DIMM-side * 1 DIMM-side/channel * 1

channel * 1 B/8 b * 1 M/1024 K = 128 MB)

•

By using 1 Gb technology in Dual Channel Interleaved Mode, the largest memory

capacity possible is 8 GB. (16 K rows * 1 K columns * 1 cell/(row * column) * 8

b/cell * 8 banks/device * 8 devices/DIMM-side * 4 DIMM-sides/channel * 2

channels * 1 B/8 b * 1 G/1024 M * 1 M/(K*K) = 8 GB)

•

Maximum DRAM address decode space is 8 GB (assuming 36-bit addressing)

•

Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of 8

bank devices)

•

Supports opportunistic refresh scheme

•

Supports Partial Writes to memory using Data Mask (DM) signals

•

Supports page sizes of 4 KB, 8 KB, and 16 KB

•

Supports a burst length of 8 for single-channel and dual-channel interleaved and

asymmetric operating modes

•

Improved flexible memory architecture

G35 Datasheet(PDF) 24 Page - Intel Corporation

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